Dreamdisk lives!

[exidyboy]

Here is one Write Data pulse on the original Dreamdisk board from the 80's. You can that the duration of the pulse is 450nS.
I find the documentation ambiguous about how you adjust the width of the Write Data pulse.

Page 8 of the TI manual for the WD2793 says that:

"Write data consists of a series of pulses set to a width approximately three times greater than the precomp adjustment."

So this implies that you need to adjust 50K variable resistor R6 to get a wide enough Write Data pulse successfully write to a Gotek or real floppy.

Elsewhere however I read that Write Compensation is only relevant to "early 8 inch drives" and irrelevant if only using minifloppies. In John's notes for the recreated Dreamdisk it says that WPW "is only for 8” Floppy drives thus no adjustment required."

So does the duration of the Write Data pulse track R6 or is it derived from the setting of RPW (Read Pulse Width) pot that "controls the phase
comparator within the data separator." (p3 of TI manual).

Could one of the experts clear this up

[johnhalk]

Hi Michael,

There is a conflict here between what the Dreamdisk manual says - i.e. R6 write pre compensation WPW setting is only required for 8” drives only.

The WD2793 datasheet states the WPW setting is required for MFM (double density drives) so this includes 5.25” drives as well.

There is procedure in the wd2793 data sheet to set the WPW value.
I would start at 100ns.

Regards,
John

[exidyboy]

Hi John,

I've swept the 5K pot R6 in minute increments from fully CCW that gives a WPW of 525nS through to fully CW that gives a WPW of 39 nS and I have not found a value that causes writes to succeed.

I will keep looking for other differences in setup or behaviour.

[exidyboy]

I've done more work comparing the write behaviour of the original and new boards. On both boards I could see the Write Gate go active low and the controller emit a string of negative going Write Data pulses to the drive. Even after checking the Write Precompensation timing again in the test mode I could not get the Write Data pulses on the 21st century recreation of the Dreamdisk controller to match the original 20th century version even though the sequence of signalling to and from the drive looks perfectly reasonable and the same.

I rechecked the logic around the 5/8 inch drive select and the ENMF (enable minifloppy) and again that all looked fine so the board isn't using different datarates for read and write.

I then investigated the clock. On my build of the new version I found that the clock input to pin 36 on the WD2793 was reading 4MHz (when the instrument would lock) and unstable rather than 2MHz. On my iteration at least, rather than a 2MHz square wave with a 50% duty cycle it looked more like a 4Mhz pulse.

It would be good to know what the clock signal looks like on other builds such as that of jltursan.

As a source of clean 2MHz clock I took the signal at pin 36 on the WD2793 on the original Dreamdisk controller and connected that to pin 12 on the socket for the 74LS92 or 74LS93 after removing the chip.

I was then able to write files to a Gotek without any further adjustment.

As noted above the original schematic indicates you could install a 74LS92 or a 74LS93. The original has a 92 soldered in and the version that John built that I have been testing has a 93. The original schematic shows pin 1 from the 92/93 going to the WD2793. This is perplexing as pin 1 is a second clock input (CLK B) not an output. However on the original board there is continuity between pin 1 and pin 12 (QA). There is no trace joining these pins on the copper side of the board but there may be a diagonal trace underneath the IC on the component side that I can't without desoldering the chip. I don't want to do that as I think this is a completely original board, purchased as a spare and never used before, so I would like to keep it in original condition.

RetroStack has taken the pin 12 output QA from the divide by 2 section of the chip as the clock source, and grounded pin 1, which all seems reasonable. If that is all correct the issue may be with the 4MHz oscillator comprised of the 4MHz xtal, a 74LS00 and some discretes.

It may just be a construction issue unique to this board which was the first one put together but the bottom line is with a clean, stable 2MHz clock input to pin 36 on the WD2793 there is no problem writing to disk.

In the image below the lower trace is a clean 2MHz signal and the top is what I was getting as input to pin 36.

IMG_8578.jpg (182.85 KiB) Viewed 125 times

[johnhalk]

Excellent work Exidyboy in identifying the issue with the write to disk not working.

I will ask Retrostack to have a look at the 4mhz/2Mhz divide by 2 clock circuit on the replica Dreamdisk.

Hopefully we can get this sorted without requiring a new pcb update/re-design.

[johnhalk]

I am taking a guess here but the 4mhz crystal on the original Dreamdisk controller could have different load capacitance specifications to the modern crystal on the dreamdisk modern replica.

Could the value of C6 on the dreamdisk modern replica be the issue ?

Modern 4MHZ Crystal specs:
https://www.mouser.com/ProductDetail/Vi ... bEMmNXtb0n


Load Capacitance and Calculator:
https://ecsxtal.com/news-resources/the- ... r-designs/

https://ecsxtal.com/crystal-load-capaci ... alculator/


I uploaded the clock circuit for the replica Dreamdisk to ChatGPT and I got the following output.

“The circuit shown uses a 74LS93 (a 4-bit binary counter) to divide a 4 MHz clock signal down to 2 MHz by using a flip-flop to divide by 2. If the output is not a clean 2 MHz clock, possible causes include:

1. Noisy or Unstable 4 MHz Input Oscillator
• If the crystal oscillator circuit (U7A, U7D, R8, R9, C6, and the 4 MHz crystal) isn’t oscillating cleanly, it can cause jitter or instability at the input, resulting in an unstable 2 MHz output.

2. Improper Oscillator Biasing
• The feedback network around U7A and U7D is critical for stable oscillation. Incorrect resistor or capacitor values (e.g., R8, R9, or C6) could cause start-up failure or ringing.

3. Poor Decoupling or Power Supply Noise
• If the +5 V supply is noisy or lacks adequate decoupling near the ICs (especially U8), it can affect logic thresholds and timing. Consider adding a 100 nF ceramic capacitor close to U8’s Vcc and GND.

4. Floating Inputs
• Any floating inputs on the 74LS93 or 74LS00 gates (U7 and U8) can cause unpredictable behavior. Ensure all unused inputs are tied to a defined logic level (preferably GND for LS series).

5. Timing Violations or Propagation Delays
• If signals are not properly synchronized or if there’s excessive loading on the outputs (e.g., long traces or high fan-out), it may distort the output waveform.

6. Incorrect Wiring
• Ensure the correct connection to divide by 2 using Q0 (pin 12 of U8). Verify that CP0 (pin 14) is connected to the NAND gate output and CP1 (pin 1) is tied to GND for independent clocking of the first flip-flop.

Suggestions for Debugging:
• Use an oscilloscope to verify the waveform at the input to U8 and at its Q0 output.
• Check if the 4 MHz oscillator is clean and symmetrical.
• Check all power pins and decoupling caps.
• Temporarily replace the 4 MHz crystal and timing components if uncertain.”

[Retrostack]

In the image below the lower trace is a clean 2MHz signal and the top is what I was getting as input to pin 36.

Do you mean pin 24 on the WD2793? Pin 36 is WPRT*, not the clock. Just want to confirm.

Is the graph you are showing the oscilloscope itself or a signal analyzer? It looks like these are too clean signals for an oscilloscope.

I rebuilt that circuit locally on a breadboard, and I do get the same issue:

IMG_3904.jpg (217.48 KiB) Viewed 70 times

The yellow line is the input at pin 14 on the 74LS93 while the green line is the output at pin 12. You can see that the green line isn't very clean. I get a similar graph on the output as the input with the same frequency (4MHz), just with a slight offset. This should be divided by two. I tried it also with a 74LS92 with the same results.

However, I noticed this small notch on the yellow input line that when you zoom in more is seen to go slightly high and drops lower and then back up. It probably surpasses the threshold for the counter to count again, resulting in two ticks for each clock cycle, getting then the same clock speed on the output, which also would explain an un-clean count signal.

Now, we just need to try to smoothen this line out. I've added a 470pF capacitor between pins 14 and GND and got a much better curve and the green line is now a 2MHz 50% duty cycle clock.

IMG_3905.jpg (224.32 KiB) Viewed 70 times

I tried with a 1pF (which barely worked) and up to 1nF (which also barely worked). Try the 470pF as well, if you have one. Otherwise try with what you have in that range and see if that fixes it. Looks like the input signal to the 74LS93 is just not clean.

[exidyboy]

In the image below the lower trace is a clean 2MHz signal and the top is what I was getting as input to pin 36.

Do you mean pin 24 on the WD2793? Pin 36 is WPRT*, not the clock. Just want to confirm.

Yes pin 24 sorry. Pin 36 is 4 pins from other corner

Is the graph you are showing the oscilloscope itself or a signal analyzer? It looks like these are too clean signals for an oscilloscope.

They are traces from the digital inputs of an Agilent 54641D Mixed Signal Oscilloscope set up for TTL thresholds so yes very clean.

I noticed that if I touched the 4MHz xtal I got a stable 2Mhz clock at the WD2793. However once connected to the Sorcerer the clock reverted back to 4MHz pulses. I tried a few things including grounding the case of the xtal and installing the 74LS00 directly into the PCB rather than in a socket. You can see that this improved things a little bit with the top trace showing the CLK input to the new board and the bottom the original. There are still bursts of errant brief pulses and read performance in fact seems to decline.

Screen Shot 2025-05-05 at 10.18.30 pm copy.jpg (245.06 KiB) Viewed 33 times

Now, we just need to try to smoothen this line out. I've added a 470pF capacitor between pins 14 and GND and got a much better curve and the green line is now a 2MHz 50% duty cycle clock.

I then added 470pF (which I only had in 0603 package ) between pin 14 (CLK A input) and pin 1 opposite which was grounded.

Screen Shot 2025-05-05 at 10.37.44 pm.jpg (213.33 KiB) Viewed 33 times

This does indeed seem to give a stable 2MHz clock comparable to the original design D6 is pin 24 on new controller board and reads as 2MHz, lower trace (D4) is same pin on an original Dreamdisk controller and gender bender board.

Screen Shot 2025-05-05 at 10.30.24 pm copy.jpg (245.53 KiB) Viewed 33 times

[exidyboy]

P.S. And yes you can SAVE files:

Screen Shot 2025-05-05 at 11.19.54 pm copy.jpg (175.56 KiB) Viewed 32 times

Screen Shot 2025-05-05 at 11.21.17 pm copy.jpg (197.95 KiB) Viewed 32 times

Screen Shot 2025-05-05 at 11.22.26 pm copy.jpg (191.94 KiB) Viewed 32 times

Screen Shot 2025-05-05 at 11.23.25 pm copy.jpg (199 KiB) Viewed 32 times

[Retrostack]

Great to hear. I already made adjustments to the board and will make this available soon. For all already created boards, this is an easy enough fix to make, rendering them working as well.

Thank you for confirming and all the initial debugging. Without your input I wouldn’t have been able to find the source.